A memory cell in a DRAM generally includes transistor and capacitors in which data is stored. Since capacitors can lose charge over time, the DRAM is periodically refreshed to recharge data stored in the memory cells. The refresh operation can involve enabling several world lines (W/L) in an active row of memory cells and sensing the bit lines for the cells. For a synchronous DRAM having 4 memory banks of cell arrays, a refresh operation may involve simultaneously activating 4-8 word lines. In contrast, during a read/write operation in the 4 memory banks, only 1-2 word lines may be activated at a time. Consequently, the amount of power drawn by, and the noise introduced into, the memory banks during a refresh operation can be substantially higher than during a read/write operation. As a result, the refresh operation itself can cause a loss of data and can lead to deterioration of the memory cells of the DRAM.
One approach to reducing the noise introduced during a refresh operation is to provide a partial refresh operation in which word lines for the memory banks are sequentially activated at time intervals of Δt and the bit lines for the memory banks are also sequentially sensed at time intervals of Δt.
An example of a partial refresh operation is provided with respect to FIG. 1. The DRAM shown in FIG. 1 includes 4 memory banks A, B, C, and D. During a refresh operation, word lines W/L_A, W/L_B, W/L_C, and W/L_D, which correspond to row addresses (or “X address”), in the memory banks A, B, C, and D are sequentially activated at time intervals of Δt. Time delay is introduced between the word lines W/L_A, W/L_B, W/L_C, and W/L_D by delay devices D1, D2, D3, and D4. In this manner, the peak noise occurring during a refresh operation may be reduced by about ¼ relative to a refresh operation in which the four word lines are simultaneously activated.
Further reduction of the peak noise during a refresh operation is desirable to improve the operational characteristics of DRAMs.